1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to an integrated circuit that has an overetch resistant local interconnect structure, and a method for making the same.
2. Description of the Related Art
Modern integrated circuits routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous individual transistors in a modern integrated circuit are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
In addition to the one or more metallization layers, modern integrated circuits also incorporate numerous routing-restricted interconnect levels commonly known as local interconnect ("LI"). LIs are used for short metallization runs such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure in the integrated circuit.
A method frequently employed to form LI structures involves a damascene process in which the substrate containing the integrated circuit is coated with a layer of dielectric material that is lithographically patterned and etched to form trenches in the dielectric layer where the LI structures will be deposited. For LI structures interconnecting transistor components, the trenches must be formed in close proximity to the components of the transistors. For example, an LI structure intended to interconnect the source or drain of a transistor requires a trench to be formed in the overlying dielectric layer that extends down to the source or drain. If the LI structure is designed to interconnect with an overlying structure, such as a metallization layer, and if alignment of the photolithographic process used to pattern the trench is perfect or nearly perfect, the trench will be patterned and etched only over the source or drain. However, LI structures are frequently used to interconnect adjacent circuit structures. Such laterally routed LI structures must pass over at least one border between the active area of the strapped transistor and its surrounding isolation trench. In addition, photolithographic processes seldom achieve perfect alignment. Lateral routing and/or misalignment result in the frequent patterning and etching of LI trenches over not only the targeted transistor structure, such as the source or drain, but also over the isolation structures that border the transistor. Since the isolation structures are frequently composed of the same or a similar type of dielectric material that is being etched to form the LI trench, the etching process may attack the isolation structures surrounding the transistor and form voids that extend to the active area of the transistor. When the LI material is ultimately deposited in the trench, conducting material fills the void and shorts the junction. The result is lower yields.
In addition to lowering yields, the overetch problem may lead to wasted electrical testing steps. The problem stems from the fact that the shorted junctions may not occur uniformly across the surface of a given wafer. As a consequence, shorted junctions may arise in the operational transistors, but not in the test structures in the wafer. The defects in the operational transistors may not be detected during the initial electrical characterization tests which are normally performed only on the test structures. Such defects may only be detected during subsequent probe testing of the operational circuits on the wafer. The result is wasted processing time.
In conventional LI processing, control of the overetch problem is attempted through manipulation of the etching process. The disadvantage of this approach is that precise control of the etching process is difficult to achieve. This is due, in large part, to the fact that the design rules for a conventional LI trench etching process are based upon an anticipated average thickness for the dielectric layer, and any underlying layers, such as TiSi.sub.2, and a Si.sub.3 N.sub.4 or oxynitride etch stop layer. In practice, however, the actual thicknesses of these layers may be less than the anticipated norm. As a consequence the etch process may remove these layers and attack the underlying isolation structure before the etch cycle is completed. Furthermore, there may be variations in the composition of the dielectric and underlying TiSi.sub.2 and Si.sub.3 N.sub.4 layers that may enable the etchant species to attack certain areas more aggressively than others and lead to overetch. The overetch problem is, as noted above, exacerbated by the fact that the dielectric layer and the underlying isolation structures are composed of the same or a related dielectric material. Consequently, once the etch stop layer is compromised, the etchant gases will readily attack the isolation structure.
The present invention is directed to overcoming or reducing one or more of the foregoing disadvantages.